1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and particularly to a manufacturing method of a semiconductor device in which the increase of contact resistance due to the absorption of boron by titanium is suppressed and the characteristics are improved.
2. Description of the Related Art
As the miniaturization of a semiconductor device advances, in the semiconductor device with a silicon substrate, a barrier metal layer made of titanium-based metal (for example, Ti, TiN, TiON, TiW, etc.) is formed before the formation of a wiring layer.
With reference to FIGS. 15 to 17, a conventional manufacturing method of a semiconductor device will be described while a power MOSFET with a trench structure is used as an example.
In FIG. 15, a p−-type epitaxial layer is laminated on a p+-type silicon semiconductor substrate 21 to form a drain region 22. After an oxide film (not shown) is formed on the surface, the oxide film at a portion of a planned channel layer 24 is etched. This oxide film is used as a mask, and boron is implanted into the whole surface at a dosage of 1.0×1013 cm−2, and then, boron is diffused to form the n-type channel layer 24.
Next, trenches are formed. A mask of a CVD oxide film of NSG (Non-doped Silicate Glass) is provided on the whole surface, the silicon semiconductor substrate is dry-etched by CF-based and HBr-based gas, and the trenches 27 are formed to pass through the channel layer 24 and to reach the drain region 22.
In FIG. 16, first, dummy oxidation is performed to form a dummy oxide film on inner walls of the trenches 27 and the surface of the channel layer 24 and to remove etching damage at the time of dry etching. The dummy oxide film formed by this dummy oxidation and the CVD oxide film are simultaneously removed by oxide film etchant such as hydrofluoric acid, so that a stable gate oxide film can be formed. Besides, thermal oxidation is performed at high temperature to round an opening part of the trench 27, and there is obtained an effect to avoid electric field concentration at the opening part of the trench 27. Thereafter, a gate oxide film 31 is formed. That is, the whole surface is subjected to thermal oxidation, and the gate oxide film 31 is formed to have a thickness of, for example, several hundred A according to a threshold.
Thereafter, a non-doped polysilicon layer is deposited on the whole surface, boron is implanted and diffused at a high concentration to raise the conductivity, and the polysilicon layer deposited on the whole surface is dry-etched without a mask so that gate electrodes 33 embedded in the trenches 27 remain.
Besides, body regions 34 for stabilizing the potential of the substrate and source regions 35 will be formed. First, n+-type impurities such as As+ are selectively ion-implanted while using a resist film as a mask, and then, the resist film is removed. Further, masking is performed by a new resist film so that the planned source regions 35 and the gate electrodes 33 are exposed, p+-type impurities such as boron are ion-implanted, and the resist film is removed.
Thereafter, an insulating film of BPSG (Boron Phosphorus Silicate Glass) or the like which becomes an interlayer insulating film and a multilayer film are deposited on the whole surface by using a technique such as a CVD method, and the implanted n+-type impurities and the p+-type impurities are diffused in the surface of the channel layer 24, so that the p+-type source regions 35 adjacent to the trenches 27 and the n+-type body region 34 between the source regions 35 are formed.
Further, a resist film is used as a mask and the interlayer insulating film is etched, so that an interlayer insulating film 36 is made to remain on at least the gate electrode 33, and a contact hole CH to a metal wiring layer 38 is formed. By this, an element region of the MOSFET is formed.
In FIG. 17, first, a high melting point metal layer 37 which becomes a barrier metal layer is formed of titanium-based material (for example, Ti/TiN, etc.), and subsequently thereto, aluminum alloy which becomes the metal wiring layer 38 is sputtered on the whole surface (see, for example, Japanese Laid Open Patent Publication No. 2003-151917).
As a metal wiring layer of a semiconductor device with a silicon substrate, aluminum-based metal material such as aluminum alloy as described above is generally used. In this case, silicon is mixed in the aluminum alloy.
However, at present, the miniaturization of elements advances, and each region is formed to be more minute. Thus, there have been problems that grains (silicon nodules) of silicon mixed in aluminum to suppress spike (mutual diffusion of aluminum and silicon) block up the source region or the body region exposed in the contact hole CH, and poor contact occurs or the substrate potential becomes unstable.
Thus, a barrier metal layer made of titanium-based metal (for example, Ti, TiN, TiON, TiW, etc.) is formed before the formation of the Al wiring layer to suppress the growth of the Si nodules in the contact hole and to prevent the mutual diffusion in the contact portion between the Al wiring layer and the semiconductor substrate surface.
Here, the element region is composed by a p-type impurity diffusion region and an n-type impurity diffusion region, and boron (B+) is generally adopted as a p-type impurity. In the element region, as described above, the metal layer including at least Ti in the undermost layer is formed as the barrier metal layer. That is, a titanium silicide layer is formed by chemical reaction of a silicon layer in which the p-type impurity is diffused and titanium.
However, there has been a problem that at the time of this reaction, boron atoms in the element region formed in the silicon substrate are absorbed by the titanium silicide layer and the surface concentration of the p-type impurity diffusion region is lowered.
For example, as described above, in the p-channel MOSFET, the source region is the region formed by diffusing boron, and when boron is absorbed by titanium silicide and the surface concentration of the source region is lowered, the contact resistance to the wiring layer as the source electrode is increased, and the element characteristics are deteriorated.
On the other hand, although not shown, in an n-channel MOSFET, boron is adopted in a p+-type body region between source regions. Since a barrier metal layer is in contact with the body region as well, boron atoms in the body region are absorbed by a titanium silicide layer.
As stated above, when the surface concentration of the body region is lowered, the substrate potential can easily become unstable, and there is a problem that deterioration of avalanche resistance is caused.
Then, a method is adopted in which boron is additionally implanted to compensate the absorbed boron and to prevent the lowering of the surface concentration of the p+-type region.
For example, FIGS. 18A to 18C show a step of additionally implanting boron. These are sectional views of a case in which in the step of forming the source region shown in FIG. 16, boron is additionally implanted.
First, n-type impurities, which form the body regions, are ion-implanted to form n+-type impurity regions 34′, and then, a mask of a resist film PR is formed, boron forming the source regions is ion-implanted into planned regions of source region formation at an implantation energy of 50 KeV and a dosage of 5×1015 cm−2, and p+-type impurity regions 35′ are formed (FIG. 18A).
Subsequently, boron is additionally implanted in consideration of the amount of absorption. That is, boron fluoride ion (BF2+) is ion-implanted at an implantation energy of 100 KeV and a dosage of 5×1015 cm−2. Here, the impurity to be the source region and the additionally implanted impurity are implanted through the gate insulating film 31. In the above case, boron fluoride having a large mass number is adopted in order to make the impurity ion stay in the vicinity of the surface. Thus, in the ion implantation of boron fluoride, an implantation energy of about 100 KeV is required so that the ion passes through the gate oxide film 31 and reaches the Si substrate (FIG. 18B).
Thereafter, an insulating film of BPSG (Boron Phosphorus Silicate Glass) or the like and a multilayer film which become interlayer insulating films are deposited on the whole surface by a CVD method, and the n+-type impurity regions 34′ and the p+-type impurity regions 35′, and the additionally implanted boron are diffused, so that the body regions 34 and the source regions 35 are formed.
Further, the contact hole CH in which the metal wiring layer is in contact with the source region 35 and the body region 34 is formed and reflow is performed.
That is, in this step, after the additional implantation of boron, a heat treatment (1000° C. or lower, about 60 minutes) at the time of film formation of the interlayer insulating film, and a heat treatment (1000° C. or lower, about 30 minutes) after the formation of the contact hole CH, that is, the two heat treatment steps are performed. Thus, the source region 35 enters more deeply than the specified depth of the source region 35 in the direction toward the bottom of the trench 27 (FIG. 18C).
As stated above, when the source region 35 is extended, the channel region formed along the trench 27 becomes short, and there has been a problem that the increase of IDSS leak and the deterioration of VDSS are caused by the short channel effect.
In the case of an n-channel type, at the time of ion implantation of the formation of the body region 34, additional implantation of boron is performed. The condition is similar to the case of the p-channel source region 35. However, also in this case, it has been found that since the reflow after the film formation of the BPSG film and the formation of the contact hole CH is performed, the ions are deeply diffused by the two heat treatment steps, the surface concentration of the body region 34 is not much increased, and boron is absorbed by titanium silicide, so that the surface concentration of the body region 34 is lowered.